This invention relates to communication systems and more specifically to high resolution frequency tuning for radio transmitters and receivers.
One of the principal components of any communication system is the ability to accurately tune to a desired frequency for signal transmission or receipt. All technological approaches for frequency tuning involve tradeoffs between system complexity and capability.
In designing radio frequency tuners for use in modern day communication applications, engineers have often relied upon the use of Direct Digital Synthesis (DDS) technology for the frequency tuning component. Unfortunately, DDS type systems are typically associated with a high quantity of spurious frequencies that are generated during normal operation. To reduce the self generated spurious frequencies, additional circuitry such as extra phase locked loops (PLLs) are added to the system. These additional PLLs serve as low pass filters reducing the wideband spurious signal content, but at the cost of added design complexity, extra components and increased power consumption.
Alternatively, one might consider use of a Vernier PLL scheme. However, by its auxiliary nature the Vernier PLL generates spurious frequency signals that must be eliminated. These spurious signals are generated by the mixing of two or more loops, such as those in a Vernier synthesizer. As with DDS based radios, significant extra design effort and materials must be spent minimizing the unwanted effects of the self generated spurious frequencies.
In order to avoid the additional circuit complexity and cost associated with the above type communication systems, it is well known to those skilled in the art of such radio design to utilize approximating synthesizer components to achieve desired tuning. An approximating synthesizer has a plurality of predetermined frequencies for transmitting or receiving that are dependent upon design parameters. An approximating synthesizer may be thought of as a device comprised primarily of one or more linked PLLs. The output frequency of the first PLL serves as the reference frequency of the second PLL. Likewise, the output frequency of the second PLL serves as the reference frequency for the third PLL. This relationship between successive PLLs continues through n, where n is the number of PLLs in the approximating synthesizer. Each PLL has a divider component in each of the reference and feedback branches. The output frequency of each PLL is a function of the values programmed into the dividers. As the reference or input frequency of a loop increases, the tune settling time decrease. Therefore, as the number of phase locked loops in an approximating synthesizer increases, the number of programmable integer multiply/divide choices also increases and hence the number of frequency selections also increases.
Unfortunately the use of approximating synthesizer based radios in applications that require high resolution tuning is inhibited since one cannot provide with reasonable circuit parameters small and regular tuning steps as required on an adjustable frequency radio. There exists a need for a relatively simple frequency tuner that can take advantage of approximating synthesizer techniques in a high resolution application.